OPECG-2009 – CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING AND INDIAN INSTITUTE OF TECHNOLOGY MADRAS
Centre for Development of Advanced Computing and Indian Institute of Technology Madras
Technology Workshop on “Optimizing Performance of Parallel Programs on Emerging Multi – Core Processors & GPUs”
To meet the High Performance Computing (HPC) challenges, the OPECG-2009 technology workshop is aimed to understand performance enhancement through software multi-threading on multi-core processors and GPUs from application point of view.
Overview
The objective of OPECG-2009 is to extract performance of sequential and parallel programs for large-scale applications on Multi-Core processors and GPUs from application perspective. The technology workshop is aimed to cover classroom lectures in Morning/Forenoon Session and four hours Hands-on in afternoon session on each day. The hands-on Session will be conducted on Multi-Core Systems, Multi Core Systems with GPGPUs/ GPU Computing Accelerators and Cluster of Multi-Core processor Systems.
The five day technology workshop is designed in two modes – Mode 1 (June 1 – 3) for three days and Mode 2 (June 4 – 5) for two days. Registration is open for five day (Mode 1 & Mode 2) programme. Exclusive registration for Mode 2 is also available and registration for Mode 1 programme is not allowed. Participants will get an opportunity to walk-through and execute some of the programs designed for Mode 1 and Mode 2 of this workshop.
Topics of Interest
Mode 1 (Three Days): Day 1-3 (June 1-3, 2009) – Prog. on Multi-Core Processors & Performance Issues
1) An Overview of Multi-Core Architectures and Prog. Environment: Multi-Core Architecture trends & Prog.; An Overview of Symmetric Multi Processing (SMP); Shared Memory Programming-Threading; System Overview of threads; Hyperthreading (HT) Technology
2) An Overview of Multi-Core Programming: Threading and Parallel Programming Constructs; POSIX Threads (Pthreads); OpenMP: Performance Solution for Threading; Intel Thread Building Blocks (TBB), Scalable Memory Allocators; An Overview of MPI 1.0/2.0 and MPI 3.0 efforts; Mixed Mode of Prog. MPI-OpenMP/TBB/Pthreads; MPI-f90/HPF
3) An Overview of Multi-Core Processors Tools and Libraries: Multi-threaded Debugging techniques; Intel-Thread Checker, Thread Profiler, Performance Analyzer; Performance of tuned Math libraries, Compiler Optimizations; Visualization tools
4) An Overview of Measuring Multi-Core Performance: Multi-Core Benchmark Criteria; Micro / Macro Benchmarks DGEMM, HPC Challenge benchmarks, Multi-threaded I/O Suites
5) Multi-Cores and Transactional Memory (TM) : TM in the OS Programming and Performance Issues – Application point of view
Mode 2 (Two days): Day 4-5 (June 4-5, 2009) – Multi-Core Processors with GPGPUs & GPU Computing
1) GPU Computing – CUDA (NVIDIA): CUDA Hardware & Software Architecture; CUDA Software Development Kit (SDK) /APIs; CUDA Tool Chain; Performance of Applications – Issues and Challenges
2) GPGPUs – Stream Programming (AMD): AMD Stream Computing Software Stack; Brook+ Programming; Performance of Applications Issues and Challenges
3) An Overview of Programmable Graphics and Open Computing Language (OpenCL): OpenCL- GPU & CPU; OpenCL Data Parallel Execution model, Performance Issues – OpenGL/GPUs & Applications
4) An overview of Hybrid Adaptive Computing – Mixed Mode of Programming: Pthreads, TBB, GPU Computing, GPGPUs
Hands-on
OPECG-2009 Hands-on Sessions (HoS) will be conducted on IIT MADRAS Cluster of Multi-Core (Dual/Quad-Core) Processor Systems, and C-DAC’s Message Passing Cluster of Multi-Core (Quad-Core) Processor Systems, Quad-Core Processor Computing platforms for Mode 1. For Mode 2 program, Multi-Core Processors with GPU accelerators (NVIDIA – GPU Computing -CUDA SDK & AMD-ATI Stream SDK) will be used.
Dates To Remember:
Workshop begins: June 1, 2009
Workshop ends: June 5, 2009
Last date for registration to workshop: May 5, 2009
Contact:
Email Address: opecg2009@cdac.in
Website:
http://www.cdac.in/html/events/beta-test/opecg/index.html
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